1. Technical Field.
The present invention relates to a semiconductor memory device, and more particularly, to a memory architecture using a tapered arrangement of local input & output (LIO) sense amplifiers.
2. Description of the Related Art.
FIG. 1 shows a block diagram of a dynamic random access memory (DRAM) core of a conventional semiconductor memory device.
From FIG. 1, one can recognize paths for reading cell data from the banks 0-2 and 2-1 in a conventional DRAM core 100 comprising a plurality of banks.
In order to read out one or a plurality of data from the memory cells of the semiconductor memory device, the data stored in the cells should be amplified in a bitline sense amplifier. The data amplified in the bitline sense amplifier are transferred to an LIO bus via a column selection line (CSL) switch, amplified in an LIO sense amplifier connected to the LIO bus, and then transferred to a global input & output (GIO) bus. According to a typical DRAM core architecture, the GIO bus is driven by the LIO sense amplifiers having the same line driving capabilities.
When the data stored in the memory cells are read out to external circuits, the cell data in the bank 0-2 should be transferred from a starting point of the GIO bus via the overall GIO bus line to the GIO sense amplifier while the cell data in the bank 2-1 should be transferred from the middle of the GIO bus via a part of the GIO bus line to the GIO sense amplifier. In other words, the path by which the data in the bank 0-2 are transferred to the GIO sense amplifier is longer than the path by which the data in the bank 2-1 are transferred to the GIO sense amplifier.
In the above condition, it is assumed that the LIO sense amplifiers have the same line driving capabilities for amplifying the cell data and transferring the amplified data to the GIO bus.
The time for reading the cell data is related to the product of the line resistance and line capacitance of the portion of the GIO bus forming the data transfer path. Therefore, as the transfer path becomes longer, the line resistance and the line capacitance are relatively increased and the time for outputting corresponding data are also increased. Based on the above facts, it is apparent that the time for reading the data from the bank 0-2 is longer than that from the bank 2-1. Similarly, the times for reading cell data from the banks 1-2, 2-2, and 3-2 are relatively longer than those from the banks 3-1, 0-1, and 1-1.
In order to compensate for such time differences, it is possible to design the driving capabilities of the LIO sense amplifiers by considering the longest one of the cell data transfer paths. However, the chip size corresponding to an amplifier, particularly a transistor for an output driving part, must be large to implement an amplifier with a large driving capability. Also, power consumption of the amplifier is increased.
Therefore, the conventional LIO sense amplifier arrangement is not appropriate for the current technical trend requiring minimization and lower power consumption.
Accordingly, it would be desirable to provide a semiconductor memory device capable of optimizing current consumption by using proper sub-bank arrangement and at least two different kinds of LIO sense amplifiers which are installed in each sub-bank and which have different driving capabilities.
According to one aspect of the present invention, a semiconductor memory device comprises: a plurality of banks, each bank comprising a pair of sub-banks; a plurality of LIO (local input & output) sense amplifiers installed in the sub-banks, the LIO sense amplifiers sensing and amplifying data stored in memory cells of the sub-banks; and a plurality of GIO (global input & output) sense amplifiers installed between the plurality of banks, the plurality of GIO sense amplifiers sensing and amplifying outputs from the plurality of LIO sense amplifiers.
Beneficially, the LIO sense amplifiers are arranged in such a way that the driving capabilities of the LIO sense amplifiers for the sub-banks arranged farther from the GIO sense amplifiers are greater than those for the sub-banks arranged nearer to the GIO sense amplifiers, and the driving capabilities of the LIO sense amplifiers are the same as each other within each particular sub-bank.
The pair of sub-banks may be diagonally arranged with respect to a center of the banks, one of the pair of sub-banks being arranged farther from a corresponding GIO sense amplifier and the other of the pair of sub-banks being arranged nearer to the corresponding GIO sense amplifier.
According to another aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of banks, each bank comprising a pair of sub-banks; a plurality of LIO sense amplifiers installed in the sub-banks, the plurality of LIO sense amplifiers sensing and amplifying data stored in memory cells of the sub-banks; and a plurality of GIO sense amplifiers installed between the plurality of banks, the plurality of GIO sense amplifiers sensing and amplifying outputs of the plurality of LIO sense amplifiers.
Beneficially, the LIO sense amplifiers are arranged in such a way that driving capabilities of the LIO sense amplifiers installed in the sub-banks arranged farther from the GIO sense amplifiers are greater than driving capabilities of the LIO sense amplifiers installed in the sub-banks arranged nearer to the GIO sense amplifiers and driving capabilities of the LIO sense amplifiers are the same as each other within each particular sub-bank.
Also beneficially, driving capabilities of the LIO sense amplifiers in a same row are the same as each other.
Each of the sub-banks may be arranged in such a way that the sub-banks of a particular bank are arranged in the same row or column on the basis of the arranged banks and diagonally arranged in the row or the column, one of the pair of the sub-banks being arranged farther from the GIO sense amplifier, and the other of the pair of the sub-banks is arranged nearer to the GIO sense amplifier.